Webcast of HP, Samsung, ANSYS, Intel and Inphi presentation at IDF 2011 for HPC applications
 

LRDIMM and the Complex Interactions between Low Latency, High Frequency, and Power

By Dr. David Wang on 02-15-2012 at 6:24 AM

In the past few years, I’ve given a few lectures and presentations on the topic of memory systems power and performance characteristics. Occasionally, I get asked the question - “why do DRAM devices consume so much power? Don’t DRAM manufacturers know that low power is very important?” On some occasions, I try to explain that most of “DRAM power” has very little to do with “DRAM”. That is, the power that can really be blamed on the volatile cells inside of DRAM devices is really just the refresh power, and in a high performance memory system inside of a typical workstations or server, refresh power is a relatively minor contributor of the overall power draw. Instead, most of the power consumed by a DRAM device are consumed by circuits such as: high speed input receivers for address and command, active termination for non-target devices on a multi-drop bus, and DLL power for timing control of data output and terminations timing. That is, much of the “DRAM power” that a give DRAM device draws is consumed by circuits on DRAM devices that provide low latency response and precision high frequency timing control. In the case that we replace “DRAM” with another type of memory – let’s call it XRAM - and we place the same low latency and high frequency operation requirements on XRAM, then in all likelihood, XRAM will consume just as much power as DRAM, if not more in the case that the per-bit data movement costs inside of XRAM is more energy intensive than DRAM.

Okay, the astute reader may ask - What does all of this have to do with LRDIMM?

Well, the answer to that question is this – the memory buffering technology on the LRDIMM opens up new and interesting possibilities in terms of re-architecting the multi-drop DDRx memory system to save power. That is, in the DDR3 LRDIMM, a single memory buffer captures command, address and data signals from the host through a connector on a multi-drop interface, then it re-drives the command, address and data signals to 36, 72 or even 144 DRAM devices. The interface between the memory buffer and the DRAM devices is essentially an embedded interface that may not need to have 36, 72, or 144 sets of active high speed drivers, receivers and timing control circuits on the LRDIMM. Rather, some of the active circuits on DRAM devices that contribute heavily to “DRAM power” may be disabled or configured to operate with relaxed requirements and draw less power. It may then be possible to replace the 36, 72, or 144 sets of active high speed circuits on the DRAM devices with a single set of active high speed circuits on the memory buffer.

One example of the new possibility of trading off timing control and power enabled by the LRDIMM is the use of Slow-Exit Mode for precharge power down. Typically, Slow-Exit Mode is not used in servers and workstation memory systems due to the fact that DRAM DLL’s may not be active in the Slow Exit Mode, resulting in imprecise timing control for On-Die Termination turn-on and turn-off times. In laymen’s terms, because of the imprecise ODT turn-on and turn-off times, using Slow-Exit Mode for precharge powerdown typically results in a large reduction of available memory bandwidth. Consequently, the Slow-Exit Precharge Power Down Mode is not often utilized except in limited configurations – for RDIMM-based memory systems. In the case of LRDIMM-based memory systems, the memory buffer is responsible for timing control on the host interface, and the timing control on the host interface is independent of the DRAM power states. Therefore, the Slow-Exit Precharge Power Down Mode can be readily utilized on the DRAM devices on an LRDIMM without impacting the termination timing on the host interface bus. In the extreme example, the DRAM devices on an LRDIMM can theoretically be placed into the lowest power self refresh states without impacting termination functionalities in a multi-DIMMs-per-channel LRDIMM memory system.

Interested in other possibilities that the memory buffer on the LRDIMM may enable to reduce power? Stay tuned.

LRDIMM Memory Capacity V.S. System Performance

By Chao Xu on 02-07-2012 at 8:01 AM

Recently I bought two 8GB DDR3 modules and put into my home game server. “Crysis 2” showed much smoother shooting action, fast presentation, and a spectacular visualization. My game score got a record high!

Why does the RAM memory capacity influence the computer performance?

Technically speaking, the RAM memory does not have any kind of influence on the processor performance of the computer, that is, the RAM memory does not increase the processing performance of the processor.

So, what is the relationship between the RAM memory and the performance?

The computer processor search for instructions are stored in the RAM memory of the computer to be executed. If those instructions are not stored in the RAM memory, they will have to be transferred from the hard disk (or from any other storage system, such as flash, CD-ROMs) to the RAM memory - the well-known process of "loading" a program.

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AMD Validates iMB™ for Opteron™ 6200 Series Platform

By Paul Washkewicz, Vice President of Marketing, Computing and Storage at Inphi on 01-30-2012 at 8:01 AM

We continue to see and increased demand for memory-management solutions and have worked closely with major OEMs to increase memory capacity, performance and speed. Today, we announced that LRDIMMs enabled by Inphi’s iMB™, have been fully validated and supported on the  new AMD Opteron™ 6200 Series processors, formerly code-named "Interlagos."  The validation provides memory vendors and systems designers the assurance that they can populate AMD Opteron 6200 Series-based systems with up to 768GB of cost-effective memory for today’s demanding enterprise and cloud-based applications in 2P servers. Check out the full press release.  

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LRDIMM Ecosystem Taking Off

By Doug Daniels on 01-23-2012 at 8:52 AM

In case you missed it over the holidays, several major industry players have announced LRDIMM-related news in the past few months.

In November and December, Intel posted successful validation results to their website for eight different LRDIMMs from five different suppliers, all using Inphi’s iMBTM. The LRDIMM modules ranged from 8GB to 32GB in capacity, and were validated at rates including DDR3-1066, DDR3L-1066 and DDR3-1333. Suppliers passing Intel’s rigorous testing included Samsung, Hynix, Crucial, Elpida and Micron.

Also in November, Micron announced a full lineup of LRDIMM offerings, including 8GB, 16GB, 32GB and 64GB varieties. SMART Modular Technologies announced a 16GB LRDIMM of their own earlier this month.

Looking for someplace to plug in your new LRDIMMs? Server maker Supermicro lists seven motherboards boasting LRDIMM BIOS support. Keep watching the LRDIMM Files blog and Inphi’s press releases for new LRDIMM announcements.

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Server Design Summit LRDIMM Presentation

Posted on 12-19-2011 at 2:25 PM

Inphi's Sameer Kuppahalli recently presented on "Introducing LRDIMM in Servers and Workstations" at the 2011 Server Design Summit. The conference was held in Santa Clara, CA Nov 29-30, 2011. You can check out his presentation by visiting: http://www.serverbladesummit.com/English/Collaterals/Proceedings/2011/20111129_S2-101_Kuppahalli.pdf

Live LRDIMM Demo at SC11

By Doug Daniels on 11-08-2011 at 9:12 AM

Developers, users and fans of High-Performance Computing systems won’t want to miss Inphi’s live LRDIMM demo at SC11 in Seattle next week, November 14th to 17th. The demo will showcase the system speed and DDR3 memory capacity made possible by the LRDIMM in HPC applications. Stop by Booth # 5300 in the Washington State Convention and Trade Center to say hello and ask any questions you have about the LRDIMM or Inphi’s iMBTM.

SC11 is the international conference for high performance computing, networking, storage and analysis. After you visit the Inphi booth, keep a sharp eye out for LRDIMM sightings elsewhere on the convention floor. See you in Seattle!

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Come listen to Inphi Speaker's presentations at JEDEC's Server Memory Forum on Nov 1~2!

JEDEC's Server Memory Forum will be held November 1-2, 2011 at the Hilton in Santa Clara, California.

Mr. Paul Washkewicz's presentation will be held on November 1 at 3:30 p.m. Pacific Time. He will be presenting:

• DDR3 Memory Buffer: Buffer at the Heart of the LRDIMM Architecture

Dr. David Wang's presentation will be held on November 2 at 1:00 p.m. Pacific Time. He will be presenting:

• A Perspective on DRAM Memory Systems: Metrics and Scaling Trends

More information and registration information may be found at the following location: http://www.jedec.org/events-meetings/server-memory-forum

See you there!

Inphi’s iMBplus – Industry’s First LRDIMM Signal Integrity Tool to Analyze and Improve System Memory Performance

By Abhishek Desai on 10-13-2011 at 7:13 PM

What are the challenges with LRDIMM debugging today? In a LRDIMM, the loading on the host controller is greatly reduced by Inphi’s Isolation Memory Buffer (iMB™) that facilitates larger memory capacities at higher frequencies. On a system platform, when LRDIMM is plugged into the memory slot, the host controller instructs the iMB to train with the DRAM behind the buffer and subsequently the host controller trains with the iMB. This procedure is completed by the BIOS at which point the memory system is ready for regular operation. Given the lack of visibility for the host controller to the ranks of DRAM hidden behind the memory buffer, any issues with initializing or training the memory system is very hard to debug.
Examples include:

• Probing difficulties on the DIMM due to inaccessible probe points.
• The number of signals that need probing to comprehend the overall functionality is large and complex.
• SI issues that occur randomly due to a bad eye margin are difficult to capture reliably.
• Memory and Buffer Vendors do not have the capability to poll the host controller for status/debug messages.
   

How does iMBplus resolve these challenges?
The system debug can be greatly improved if training and initialization issues are isolated as pre-buffer related or post-buffer. This is when iMBplus becomes a critical tool in the debugging process. Inphi’s iMBplus is a unique debug analysis tool that offers the following features and benefits:

• Margining capability of the post buffer interface to allow customers to analyze the signal integrity of the DRAM interface as comprehensively as a pre-buffer interface, improving the quality of the LRDIMM.
• User-friendly programmability of the iMB control words and logging capability of the post-buffer control status registers to simplify the analysis of any failures on the post-buffer DRAM interface.
• Eliminates the need for DIMM vendors to perform repeated testing across various memory controllers which improves the overall efficiency of the testing process and lowers the test cost. 

Taking a Closer Look
iMBplus has two main components. One part consists of the core software that is loaded on an EPROM chip in the same socket as the regular BIOS. The second part is the client software that runs on a PC with Windows XP or Widows 7. The two parts talk to each other through a RS232 serial interface cable. The core software in turn communicates with the iMB on every DIMM of the memory socket and passes on the commands it receives from the client software.

Once the iMBplus is installed on the system one can probe all internal registers in the iMB for debug information. One can also run MEMBIST that is built into the iMB to check DRAM robustness. One example where system level debug is needed is when the host controller fails a boot test due to host memory test failures. By running iMBplus and iMB MEMBIST, one can isolate the issue to be a post-buffer (iMB-DRAM) related problem or a pre-buffer (host-iMB) related problem. This helps to focus resources and get to the root cause faster. iMBplus is also used to check eye margins on the post buffer side. One can validate a DIMM to be healthy if enough margins are found on either side of trained values. Voltage margins are also available on the DRAM side. iMBplus can be used not only for debug but for obtaining general info on the system setup like reading the SPD bytes on the DIMM or reading the settings of MRS commands from the iMB.

Let me know your thoughts or send me any questions that you have!

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LRDIMM, Memory System Virtualization

By Chao Xu on 09-30-2011 at 2:13 PM

LRDIMM was one of biggest highlights at IDF this year. As mentioned in an Executive Brief titled, "Managing Memory Bandwidth Scaling Challenges with LRDIMM and Memory Buffering," "LRDIMM benefits a broad segment of the capacity enterprise server and workstation market in terms of higher capacity with performance and cost optimization, while allowing organizations of all sizes to take full advantage of multi-core and virtualization technologies". In summary, LRDIMM provides the richest features for memory system virtualization.

Cloud computing makes productivity easier by giving everyone endless ways to work and collaborate from anywhere at any time and on any device. I can own way less and do way more. Virtualization is one of the key technologies to enable the computing cloud. LRDIMM technology gives the same power for enterprise servers to implement memory system virtualizations.

The enterprise server memory systems are mainly determined by two interface technologies. One is the memory controller interface, i.e. host interface. The other is the DRAM interface. Usually the host interface is “matched” with the DRAM interface in different DRAM generations, such as DDR2, DDR3 etc. But this “match” is only good for a certain amount of time. These two interfaces are developed in different pace and eventually they are out of sync. LRDIMM technology will bridge this gap and separate the host interface from the DRAM interface and virtualizes the server memory system!

Enough talk about the concepts. Let me give you some concrete examples. One of LRDIMM features is called “rank multiplication.” Usually the host memory controller can only supply limited number of “chip select” signals in each generation due to package pins limitation. This “chip select” signals determine how many physical memory ranks can be installed on the server memory system, i.e. memory capacity. Due to DRAM technology advances, more memory chip dies can be stacked in one package to increase memory capacity. The number of ranks in one package chip is growing faster than that host memory controller can access. LRDIMM memory buffers hide the DRAM interface from the host interface and implements the host interface as small number of ranks, while implementing the DRAM interface as 2x or 4x number of ranks, i.e., virtualization of host interface from DRAM physical interface.

Another very useful feature of LRDIMM technology is called “Nibble Merge”. There are two main different DRAM interface. One is “x4” and the other is “x8”. “x4” DRAM chip has one differential strobe signal pair controls 4 data lines. “x8” DRAM chip has one differential strobe signal pair controls 8 data lines. There are different attributes for each technology. Different applications need different interfaces. In RDIMM, after the memory module is manufactured, the host memory controller has no choice to select “x4” or “x8” and has to “match” the DRAM interface. In LRDIMM technology, memory buffers separate the host interface from the DRAM interface. Memory buffer implements the host interface which can be “x4” or “x8” regardless of the DRAM interface and selectable by a register bit. This feature provides flexibility for the system memory controller to optimize the system power and performance based on applications.

There are many additional unique and intelligent features in LRDIMM memory buffers, such as Inphi’s iMB™, which is not only fully compliant with JEDEC standard, but also has rich proprietary features which can be used in the cloud computing and virtualizations!

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Managing Memory Bandwidth

By Sameer Kuppahalli on 09-13-2011 at 3:43 PM

IDC just completed an Executive Brief that we have been working with them on, titled, “Managing Memory Bandwidth Scaling Challenges with LRDIMM and Memory Buffering.” This Executive Brief examines the critical role of the memory buffer in reducing the loading on the data signals and populating more ranks of physical memory on a server system. The result is a Load Reduced DIMM (LRDIMM) powered by a memory buffer that delivers significantly higher memory capacity and bandwidth. Check it out and let me know what you think!

Just a reminder that if you are attending IDF this year to come see us and other industry leaders present on the LRDIMM Hot Topic session on Wed Sept 14 at 4:25 pm in room 2006. And don’t forget to stop by our booth #717 and see our demo that showcases the benefits of 32GB LRDIMM to a memory and compute intensive application in a virtual environment. Take the Inphi Challenge and win a free iPOD Nano!

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LRDIMM Coming to IDF 2011

By Doug Daniels on 09-08-2011 at 8:43 AM

Inphi and the LRDIMM will be making an appearance at the Intel Developer Forum (IDF) next week in San Francisco, September 13th to 15th. Inphi’s engineers have been busy assembling a live demonstration that will show off the system speed and capacity made possible by LRDIMM technology, so stop by Booth # 717 to see for yourself. Drop by to say hello, ask any questions you have about the LRDIMM or Inphi’s iMBTM, and enter our daily drawing to win an Apple iPod nano. If you’ve been reading about the LRDIMM here on the LRDIMM Files blog, be sure to let us know.

Inphi will also be participating in the Hot Topic Q&A session at 4:25 PM on Wednesday, September 14 in Room # 2006. Several other industry leading companies, including Intel, HP, ANSYS, and Samsung will join us for the question and answer session on the value of LRDIMM technology in enterprise applications. If you’ve been wondering how the LRDIMM will impact your next generation server deployments, be sure to attend this session and ask the experts.

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LRDIMMs for the Cost Sensitive

By Victor Cai on 08-23-2011 at 2:06 PM

I hope everyone has been enjoying these LRDIMM posts.  Today, I would like to introduce everyone to a new class of DIMM that is made possible by the iMB.  These modules open the possibility to design large nonstandard size DIMM while taking advantage of lower cost DRAM components.  Calculations show around 20% cost advantage over traditional LRDIMM.  Significant shipped volumes of server today are larger 2U and 5U system.  Cost is a major driving factor on these sales, so this large DIMM design becomes very attractive when customers are looking at cost and performance.  Thermal management also improves because of larger surface area for heat dissipation removes the need for heat sink.   Not everyone can take advantage of this module but for those individuals that can, it provides a big opportunity to build large capacity systems at an affordable price. If you would like more information please feel free to contact me!

LRDIMM has Lower Latency than RDIMM!

By David Wang on 08-09-2011 at 5:06 PM

At first glance, the statement that “LRDIMM has lower latency than RDIMM!” sounds unbelievable and counterintuitive. However, I will assure you that the statement is indeed true.

As described previously in other posts and in the whitepaper on the LRDIMM blog site, the buffering and re-driving of the data signals enable the LRDIMM to support more DRAM devices on the memory module, and for the entire memory module to operate at higher data rates. The key to the LRDIMM-has-lower-latency-than-RDIMM claim lies in the fact that an LRDIMM memory system can operate at higher data rates than the comparably configured RDIMM memory system. Consequently, a higher data rate LRDIMM-based memory system can overcome the latency burden of having to buffer and re-drive the signals, and attain lower access latency compared to a lower data rate RDIMM-based memory system.

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LRDIMM, Server System Friend

By Chao Xu on 07-29-2011 at 5:23 PM

In previous LRDIMM Files, Doug Daniels gave a good introduction of LRDIMM and its basic features. I will focus more about LRDIMM unique advantages on server systems and talk about how LRDIMM dramatically increases server system memory capacity while simplifying server system design.   

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As LRDIMM Adoption Gains Momentum

By Sameer Kuppahalli on 07-24-2011 at 8:03 AM

As LRDIMM adoption gains momentum, I want to highlight the major market segments and how this technology will bring about the benefits. To start, I would first like to point out that the LRDIMM value proposition can be summed up as capacity/performance, performance/watt and capacity/$. At the core of the LRDIMM technology is not just the load reduction aspect, but also that it offers higher capacity using the mainstream DRAM technology.

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LRDIMM Features

By Doug Daniels on 07-19-2011 at 10:24 AM

Welcome back to Inphi’s LRDIMM Files! Last week I introduced what the LRDIMM technology is all about so this week I thought I would touch on some of the key features and benefits. In addition to maximizing system memory capacity and speed, the LRDIMM architecture enables a number of useful features for the end-user in both testing and operational modes.  The LRDIMM’s memory buffer, such as Inphi’s iMB, provides several useful features including DRAM and LRDIMM test features such as transparent mode and MemBIST (Memory Built-In Self-Test) functionality, VREF (voltage reference) margining for both the data (DQ) and Command/Address (CA) busses, an optional out-of-band SMBus (Serial Management Bus) interface for LRDIMM configuration and status registers, and an integrated temperature sensor.    A bit more information on each of these features is provided below.

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Introducing the LRDIMM

By Doug Daniels on 07-08-2011 at 3:43 PM

Welcome to Inphi’s new LRDIMM blog!  The purpose of this blog is to introduce you to the LRDIMM, a new type of memory module for high capacity servers and high performance computing platforms.  LRDIMM is an abbreviation for Load Reduced Dual Inline Memory Module, the newest type of DIMM supporting DDR3 SDRAM main memory.  The LRDIMM is pin-compatible with existing JEDEC-standard DDR3 DIMM sockets, and supports higher system memory capacities when enabled in the system BIOS.  Existing RDIMM (registered DIMM) memory technology forces end-users to make tradeoffs between memory capacity and operating speed, and is beginning to fall short of ever-increasing user demands for higher capacity.  The LRDIMM overcomes these obstacles, enabling higher capacity systems running at the highest operating speeds.  

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