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LRDIMM Features

By Doug Daniels on 07-19-2011 at 10:24 AM

Welcome back to Inphi’s LRDIMM Files! Last week I introduced what the LRDIMM technology is all about so this week I thought I would touch on some of the key features and benefits. In addition to maximizing system memory capacity and speed, the LRDIMM architecture enables a number of useful features for the end-user in both testing and operational modes.  The LRDIMM’s memory buffer, such as Inphi’s iMB, provides several useful features including DRAM and LRDIMM test features such as transparent mode and MemBIST (Memory Built-In Self-Test) functionality, VREF (voltage reference) margining for both the data (DQ) and Command/Address (CA) busses, an optional out-of-band SMBus (Serial Management Bus) interface for LRDIMM configuration and status registers, and an integrated temperature sensor.    A bit more information on each of these features is provided below.

Transparent mode:   For module testing purposes, the memory buffer can be placed in transparent mode, where it acts as a simple signal re-drive buffer and passes commands and data directly through to the DRAM devices.    

MemBIST:  For DRAM initialization and component testing purposes, the LRDIMM’s memory buffer supports a MemBIST (Memory Built-In-Self Test) function, enabling exhaustive at-speed testing of the DRAM devices.  Testing can be performed at full operational speed, using either in-band (Command/Address bus) or out-of-band (SMBus) access.

VREF margining:  LRDIMMs can use externally supplied voltage references for data (VREFDQ) and Command/Address signals (VREFCA), or supply the voltage references internally from the memory buffer. In the case where VREF is provided by the memory buffer, the voltage levels can be controlled by the host though the memory buffer’s configuration registers. The programmable voltage references enable an LRDIMM memory system to utilize independent VREF voltage references for the host-to-memory buffer interfaces and the memory buffer-to-DRAM interfaces.  This independent VREF margining capability allows module and system suppliers to separately characterize and therefore guarantee the robustness of the signaling interfaces of the LRDIMM memory system.

SMBus interface:  The memory buffer supports an out-of-band serial management bus to read and write configuration and status registers.

Temperature sensor:  The memory buffer contains an integrated temperature sensor that is updated eight times per second and is accessible at any time through the SMBus.  The memory buffer’s EVENT_n pin can be configured as an interrupt back to the host to indicate high temperature events.

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