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LRDIMM has Lower Latency than RDIMM!

By David Wang on 08-09-2011 at 5:06 PM

At first glance, the statement that “LRDIMM has lower latency than RDIMM!” sounds unbelievable and counterintuitive. However, I will assure you that the statement is indeed true.

As described previously in other posts and in the whitepaper on the LRDIMM blog site, the buffering and re-driving of the data signals enable the LRDIMM to support more DRAM devices on the memory module, and for the entire memory module to operate at higher data rates. The key to the LRDIMM-has-lower-latency-than-RDIMM claim lies in the fact that an LRDIMM memory system can operate at higher data rates than the comparably configured RDIMM memory system. Consequently, a higher data rate LRDIMM-based memory system can overcome the latency burden of having to buffer and re-drive the signals, and attain lower access latency compared to a lower data rate RDIMM-based memory system.

This figure shows the random access latency measurements of a Quad-rank RDIMM and a Quad-rank LRDIMM in the same system. It shows that when operating at the same data rate, the Quad-rank LRDIMM has approximately 5 ns longer latency than the Quad-rank RDIMM. However, it also shows that the random access latency of both the LRDIMM and RDIMM memory systems decreases with increasing data rate. Consequently, when the highest-speed-bin RDIMM memory system, operating at 1066 MT/s, is compared to an LRDIMM memory system operating at 1333 MT/s, the LRDIMM memory system operating at 1333 MT/s is shown to have the lowest access latency compared to an RDIMM memory system.

For the knowledgeable readers that find the latency measurements itself presented in the first figure to be counter-intuitive, let me provide a more detailed explanation of the phenomenon that enable the (higher operating data rate) LRDIMM memory systems to enjoy lower access latency than (lower operating data rate) RDIMM memory systems. 

This figure shows the block diagram of a modern processor where the memory controller is integrated into the processor package. It shows that the entire memory system, including the memory controller and the memory modules, operate in the same clock domain. That is, when a memory request is generated by the processor core and sent to the memory controller, the request is decoded, the physical address mapped into memory address, and the request itself broken up into DRAM commands and scheduled. The entire memory controller is in essence a sophisticated state machine that performs the action of DRAM command scheduling while operating at the same core frequency as the memory device that it is scheduling. Consequently, as the memory module operates at higher data rates, the memory controller core also operates at the higher frequency. The higher frequency means that memory request is processed faster, and the application sees the benefit of lower memory access latency.

In essence, a higher data rate LRDIMM memory system enables memory requests to traverse through the memory controller at a higher frequency, enjoying great low latency benefits, overcoming the latency overhead of the data buffering on the LRDIMM, and resulting in net reduction in access latency compared to an RDIMM memory system that operates at its maximum (1066 MT/s) frequency.

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