Enterprise Memory for EnergyStar Systems

Thursday, 12 November 2009

With the release of the energy star rating for compute servers, there has been a number of approaches to meet the requirement and increase density & performance.  Standards communities such as JEDEC, the 40G/100G networking associations are currently finalizing adoption of the the iMB (Isolation Memory Buffer) technology for new high performance memories.  The use of this technology creates a new class of memory module called the LRDIMM (Load Reduced Dual Inline Memory Module).  This technology was developed by Inphi, a ten year old high speed  analog semiconductor company from Sunnyvale CA.

The key issue for modern data centers is how to address the growing performance needs of the users in an ever decreasing power budget.  The LRDIMM technology is supported by a custom logic controller chip that handles the buffering through a standard load interface.  The key is a high signal integrity based memory buffer that has a fixed load to the bus independent of the memory depth behind it.  This allows configurations that would be using one (1) bank of memory, can now support up to 8 banks of memory in the same speed and bus power.  For compatibility and optimization with multi-core CPUs , the iMB interface includes task based duty cycle reduction and deep memory idle states.  The iMB parts use dynamic termination of the memory banks to manage power for DDR3 operation at 800, 1066, 1333 bus speeds at both 1.35v and 1.5v operation.  These features are also supported through the new JEDEC 1600 spec and will be scalable to DDR4 3200 applications.

The LRDIMMs are being built by Hynix Samsung, Micron, Naya and others using the Inphi chips in Q1 ‘10.  The products are currently only for the Enterprise class EnergyStar applications as the Inphi chip that is being used costs about $25US in 100k qty.  The advantage of the technology is the power reduction and density/performance improvement while still maintaining the 10-12 BER and supporting a single chip/ single cycle load for both command and address signals.

PC

Return to top