INCU877
DDR2 - 1:10 Zero Delay Clock Buffer

Applications

• DDR2-400, 533, 667, and 800 Registered DIMMs
• High Performance Workstations
• Mid and High Performance Servers

Features

• Operates with 200, 266, 333 and 400 MHz clocks
• Exceeds all JESD82-8 performance specifications for DDR2-400 and DDR2-533
• Exceeds all JESDxx-x performance specifications for the CUA877 & CUA878 at all DDR2 rates
• Available in a 52 Ball VFBGA leaded, “Green” and Lead-Free VFBGA Package
• Latch up exceeds JESD78 class 2
• ESD protection exceeds JESD22
• Passed Intel Validation

Description

The INCU877/INCU878 is a high performance, low skew, PLL-based, zero delay buffer that distributes a differential input clock signal to ten differential clock outputs and one differential feedback clock output. The INCU878 is a fast-lock version of the INCU877.

The clock outputs are controlled by the input clock, the input feedback (reference) clock, the LVCMOS control inputs, and the analog power supply.

When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock input pins are logic low, the device enters a low power mode. A logic circuit on the clock input pins, independent from the input buffers, detects the logic low levels and places the part in a low power state where all the outputs and the PLL are off. When the inputs transition from being both logic low to being a differential signal, the PLL is turned back on, the inputs and outputs are enabled, and the PLL obtains phase lock between the input feedback clock pair and the input clock pair, within the specified stabilization time.

The INCU877/INCU878 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.

For more information about the INCU877 or other Inphi products, please click here and enter your email address for product downloads. New users must first complete our product request form.

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