INSSTE32882UV
1.5/1.35/1.25V DDR3 Registering Clock Driver with Parity Checking

Applications

• Mid and High Performance Servers
• High Performance Workstations
• High Reliability & Telecom Systems

Features

• Single Register Quad Rank RDIMM support
• Meets or exceeds all JESD82-29 performance specifications for DDR3(L)-800/1066/1333/1600 and DDR3-1866 rates
• Meets or exceeds all JESD82-29 performance specifications at 1.5V and 1.35V.
• Meets or exceeds all JESD82-29 performance specifications at 1.25V. (Specifications highlighted in blue exceed JEDEC standards)
• Exceeds JEDEC re-driven dynamic clock offset specification (t_DYNOFF)
• Exceeds JEDEC jitter requirements
• Supports external VREF margin option
• Supports all JEDEC lower power modes including weak-drive mode
• ESD protection exceeds JESD22
  • HBM – 4000V
  • CDM – 500V
  • MM – 300V
• Latch-up exceeds JESD78 class 2
• Backward compatible with DDR3 and DDR3L R-DIMM modules
• Supports custom RDIMM modules via programmable driver characteristics
• Available in 176 TFBGA Eco-Friendly “Green” Package
  • 8.00 mm x 13.50 mm (MO-246F)

Description

This 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for 1.5 V, 1.35 V or 1.25V V_DD operation.

All inputs are 1.5/1.35/1.25 V CMOS compatible. All outputs are 1.5/1.35/1.25V CMOS drivers optimized to drive single/multi- terminated traces in DDR3 RDIMM. The clock outputs Yn and Yn# and control outputs QxCKEn, QxCSn# and QxODTn can be driven with a different strength and skew to compensate for different loading and to equalize signal travel speed.

The INSSTE32882UV has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN#) input. When the QCSEN# input pin is pulled HIGH (or open), the component has two chip select inputs, DCS0# and DCS1#, and two copies of each chip select output, QACS0#, QACS1#, QBCS0# and QBCS1#. This is "QuadCS disabled" mode. When the QCSEN# input pin is pulled LOW, the component has four chip select inputs, DCS[3:0]#, and four chip select outputs, QCS[3:0]#. This is "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0]# will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]# will indicate all of the chip select outputs.

The INSSTE32882UV operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going HIGH, and CK# going LOW. The data could be either re-driven to the outputs once exactly one of the input signals DCS[n:0]# is driven LOW, or the data could be used to access device internal control registers when certain input conditions are met.

Based on control register settings the device can change its output characteristics to match different DIMM net topologies. The timing can be changed to compensate for different flight time of signals within the target application. Power consumption can be reduced by disabling unused outputs.

To aid our customers in optimizing their high-volume manufacturing process using the TFBGA176 package, Inphi has compiled an application note containing guidelines on the most important aspects of reflow. To optimize SMT yield and avoid pitfalls, please click here to view the SMT Reflow Guidelines Application Note.

For more information about the INSSTE32882UV or other Inphi products, please click here and enter your email address for product downloads. New users must first complete our product request form.

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