INSSTU32866
DDR2 - Configurable Registered Buffer

Applications

• High Performance Workstations
• Mid and High Performance Servers
• High Reliability Systems

Features

• Exceeds all JESDxx-x performance specifications for DDR2-400 and DDR2-533 rates
• Exceeds all JESDxx-x performance specifications for DDR2-667, DDR2-800 rates
• Supports RDIMM modules E, F, G, H, and J
• Complies with DDR2 SDRAM Over/Undershoot specification as defined in JESD79-2
• Available in a 96 Ball TFBGA leaded, lead-free and “Green” Package types
• Pull-down resistors on all data and parity inputs
• Latch up exceeds JESD78 class 2
• ESD protection exceeds JESD22
• Passed Intel Validation

Description

The SSTU32866 is a configurable 25-bit 1:1 or 14-bit 1:2 register and is designed for nominal 1.8V power supply operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The INSSTU32866 operates with a differential clock input.

In typical Registered DIMM applications, the outputs on these devices can each drive up to 10 SDRAM input loads.

INSSTU32866 supports low-power standby mode. When activated, the clock, data, and reference voltage (VREF) input receivers are disabled and floating clock, data, and reference inputs are allowed. Additionally, all registers are reset, and all outputs are forced low.

The INSSTU32866 continually evaluates parity of the data inputs and a parity input bit generated by the memory controller.  When the data inputs are left floating, they are internally pulled down to ground by large internal resistors. This eliminates the need for on module termination resistors, simplifying assembly and saving costs.

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