INSSTU32S865
DDR2 Registered Buffer with Parity Checking

Applications

• High Performance Workstations
• Mid and High Performance Servers
• High Reliability Systems

Features

• INSSTU32S865 meets or exceeds all JESD82-9 performance specifications up to DDR2-533 rates
• INSSTUA32S865 meets or exceeds all JESDxx-x performance specifications up to DDR2-667 rates
• INSSTUB32865 and INSSTUB32865H meets or exceeds all JESDxx-x performance specifications up to DDR2-800 rates
• INSSTUB32865H outputs drive up to 50% more load capacitance for heavily loaded RDIMMs
• Support RDIMM module D, V, Y, and other similarly configured modules
• Available in a 160 Ball TFBGA “Green” Package
• Complies with DDR2 SDRAM Over/Undershoot specification as defined in JESD79-2
• Pull-down resistors on all data and parity inputs
• Single Die solution provides lower input capacitance loading
• Latch up exceeds JESD78 class 2
• ESD protection exceeds JESD22
• Available in Industrial Temperature Range (-40 °C to +85 °C)

Description

 

The INSSTU32S865 is a 28-bit 1:2 registered buffer with parity and is designed for 1.7V to 1.9V VDD operation.  Unless specifically called out, any reference to the INSSTU32S865 refers to all four versions.  All clock and data inputs are compatible with the JEDEC standard for SSTL_18.  The control inputs are LVCMOS.  All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2DIMM load.

The INSSTU32S865 operates from a differential clock (CK and CK).  Data are registered at the crossing of CK going high, and CK  going low.  The device supports low-power standby operation.  When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed.  In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low.  The LVCMOS RESET input must always be held at a valid logic high or low level.  To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.  In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK.  Therefore, no timing relationship can be guaranteed between the two. 

The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when both DCS0 and DCS1 are high.  If either DCS0 or DCS1 input is low, the Qn outputs will function normally.  The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs low and the PTYERR output high.  If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs.  The INSSTU32S865 includes a parity checking function.  They accept a parity bit from the memory controller at its input pin PARIN, compare it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active low).

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