32821BR
32 Gbps Bit Error Ratio Receiver Reference Board

Applications

• Measurement of up to 32 Gbps serial data using low cost 10 Gbps instruments:
  • 100G Coherent DP-QPSK: 4 x 32 Gbps data streams
  • 802.3ba 100 GbE: 4 x 25 Gbps data streams
  • 40G DQPSK with 2 x 22 Gbps data streams
  • 17G Fiber Channel

Features

• Data Input is Direct-Coupled with Input Sensitivity of 100 mVpp single-ended or differential
• Clock Input Direct-Coupled with Input Sensitivity of 200 mVpp single-ended or differential
• 0.1 – 32 Gbps operation with high clock phase margin
• Down-Converts input data stream to a ¼ rate low- speed data stream
• Toggle switches or header for output selection control between four low-speed data streams
• Buffered high-speed data output for clock recovery
• 2.4 mm connectors for high-speed data and clock
• Super SMA connectors for low-speed signals
• On Board Supply Regulation
• Dimensions (4”H x 8”W x 7”L)

Description

The 32821BR is a 32 Gbps Bit Error Ratio Receiver designed to down-convert a high-speed data stream of up to 32 Gbps into a low speed data stream of up to 8 Gbps each. This enables the use of low cost 10 Gbps instruments to test signals of up to 32 Gbps.

The High-Speed Data Input (HSDINp/n) and the High-Speed Clock Input (HSCKINp/n) are direct coupled to the 50717CF pre-amps and can be driven either single-ended or differential. A buffered copy of the HSDIN and HSCKIN signals is provided via the differential High-Speed Data and Clock Outputs (HSDOUTp/n & HSCKOUTp/n). The data outputs can be used to drive an external clock recovery unit (CRU), or to monitor the high-speed data signal.

Another buffered copy of HSDIN & HSCKIN is driven into the 5081DX where it is deserialized (demuxed) into four ¼ rate data streams. The user can easily select between the four low-speed output data streams (DOUT[0:3]) to be output on the differential, Low-Speed Data (LSDOUT4p/n) Output using the two toggle switches, or via two digital control bits through the Output Selection Control connector. A ¼ rate clock (up to 8 GHz) is provided through the differential Low-Speed Clock Outputs (LSCKOUT4p/n).

The high-speed I/O to the 50717CF pre-amps utilize microwave V-connectors (1.8 mm) into the metal packages. The low-speed I/O utilizes edge-launch, Super SMA connectors on the board.

The 32821BR can be powered via an AC/DC power adapter (supplied) or via a bench power supply with banana cables.

For more information about the 32821BR or other Inphi products, please click here and enter your email address for product downloads. New users must first complete our product request form.

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