INSSTE32882LV

DDR3(L) Registering Clock Driver with Parity Checking

Applications

• Mid and High Performance Servers
• High Performance Workstations
• High Reliability & Telecom Systems

Features

• Single Register Quad Rank RDIMM support
• INSSTE32882LV-GS02 meets or exceeds all JESD82-xx performance specifications for DDR3(L)-800/1066/1333/1600 rates at 1.5V and 1.35 V VDD. (Specifications highlighted in blue exceed JEDEC specifications)
• Operational at DDR3(L)-1866 rates
• Exceeds JEDEC re-driven dynamic clock offset specification (tDYNOFF)
• Exceeds JEDEC Jitter requirements
• Supports custom RDIMM modules via programmable driver characteristics
• Supports existing RDIMM modules
• Supports all JEDEC lower power modes including weak-drive mode
• ESD protection exceeds JESD22
  • HBM – 4000V
  • CDM – 500V
• Latch-up exceeds JESD78 class 2
• Available in two 176 TFBGA Eco-Friendly “Green” Package types
  • 8.00 mm x 13.50 mm (MO-246F) or
  • 6.00 mm x 15.00 mm (MO-246B

Description

This 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for 1.5 V or 1.35 V  VDD operation.
All inputs are 1.5/1.35 V CMOS compatible.  All outputs are 1.5/1.35 V CMOS drivers optimized to drive single/multi- terminated traces in DDR3 RDIMM.  The clock outputs Yn and Yn# and control outputs QxCKEn, QxCSn# and QxODTn can be driven with a different strength and skew to compensate for different loading and equalize signal travel speed.
The INSSTE32882LV has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN#) input.  When the QCSEN# input pin is pulled HIGH (or open), the component has two chip select inputs, DCS0# and DCS1#, and two copies of each chip select output, QACS0#, QACS1#, QBCS0# and QBCS1#.  This is the "QuadCS disabled" mode.  When the QCSEN# input pin is pulled LOW, the component has four chip select inputs DCS[3:0]#, and four chip select outputs, QCS[3:0]#.  This is the "QuadCS enabled" mode.  Through the remainder of this specification, DCS[n:0]# will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0]# will
indicate all of the chip select outputs.

The INSSTE32882LV operates from a differential clock (CK and CK#).  Data are registered at the crossing of CK going HIGH, and CK# going LOW.  The data could be either re-driven to the outputs once exactly one of the input signals DCS[n:0]# is driven LOW or it could be used to access device internal control registers when certain input conditions are met. 

Based on control register settings the device can change its output characteristics to match different DIMM net topologies.  The timing can be changed to compensate for different flight time of signals within the target application.  By disabling unused outputs the power consumption is reduced.

Return to top