New Cortina Octal 15G EDC PHY Sets Industry Benchmark for Density, Low Power and Latency
Sunnyvale, Calif., December 3, 2012 — Cortina Systems, Inc. (Cortina®), delivering innovative technologies that link people and networks worldwide, today announced the industry’s first 28nm EDC PHY architecture. This next generation architecture becomes the technological foundation for future Cortina 25G and multi-level PAM products. The architecture is designed to drive dramatically lower power and support higher bandwidth to scale to 100G and 400G applications. The density of the 28nm technology will enable higher port counts and increased faceplate and backplane bandwidth for next generation data center, carrier and enterprise systems.
The first member of this architecture is the CS4343 Octal 15G Electronic Dispersion Compensation (EDC) device. The CS4343’s baseline architecture leads the industry less than 1 nsec latency in a 17mm x 17mm package, while lowering power consumption by 50% over previous generations. The CS4343 provides a wide operating frequency range from 1 to 15Gbps, and support for all the major standards used in data centers, storage, high performance computing, and wireless backhaul applications including 1GbE, 10GbE, 40GbE, 100GbE, InfiniBand, Fibre Channel, CPRI and OBSAI. This comprehensive capability allows system designers to solve a wide range of applications with the same device.
“Data centers are being upgraded to handle the exponential growth in bandwidth. System vendors are looking for solutions to meet restrictive size, power, and density constraints,” said Scott Feller, director at Cortina Systems, Inc. “28nm technology enables Cortina to develop a base platform architecture that meets system vendor requirements today and in the future while keeping a small foot print, increasing the supported data rate to 15G, while reducing power consumption by 50% over current production parts.”
“Latency, power, density, and cost are the critical differentiators for system vendors developing 10G switches for data center, storage, and financial markets,” commented Dale Murray, Principal Analyst at LightCounting, a market research company focusing on optical interconnects. “This is driving the need for high port density, low latency and power, and high feature integration in all components that go into these switches.”
The CS4343 PHY functionality supports eight full-duplex 10G links or two full-duplex 40G links. The device has a wide operating frequency range covering 1GbE, 10GbE, 1G FC, 2G FC, 4G FC, 8G, 16G FC, Infiniband SDR, DDR, QDR and FDR, and CPRI Options 1 to 7. EDC capability allows the device to operate with linear SFP+/QSFP optical modules to Direct Attach Copper, and 10GBase-ZR and DWDM SMF applications. The device is fully compliant to 10G SFP+, 802.3ba 40G and 100G nPPI, and nAUI specifications. The fully autonomous device does not require external processors to control the convergence or dynamic adaption of the dispersion compensation. The CS4343 also integrates the auto-negotiation and coefficient training functionality for 40G CR4 applications, and rate negotiation 16G Fibre channel, for seamless interoperability with existing equipment.
The CS4343 includes an integrated 2×2 switch enabling redundant backplane and faceplate applications without needing an external crossbar device. The integrated switch functionality supports 1+1 protection switching and broadcast functionality in both directions. The device supports link quality monitoring for the inactive redundant link to enable fast switching. In addition, the CS4343 has a fully symmetric architecture with EDC capability on both ingress and egress directions. This enables applications such as translation from KR4 backplane to CR4 cable in blade server designs using a single device, reducing system cost.
The CS4343 has integrated AC coupling capacitors, and supports reference clock free operation to reduce overall system BOM cost. The device also includes capabilities such as real time eye monitoring, loopbacks, PRBS generators and checkers, and hardware interrupt and GPIO pins for test and debug purposes.
The Cortina CS4343 device is currently sampling.