Polaris™ Gen2 PAM4 platform is the industry’s first 50G, 28Gbaud PAM4 DSP solution based on low-power 7nm CMOS technology. Polaris Gen2 builds on the innovation of Inphi’s market-leading, field-proven Polaris Gen1 PAM4 platform, providing even higher levels of integration and lower power for high-performance hyperscale data center, cloud computing and emerging AI applications. The new Gen2 platform provides optical network developers with a best-in-class low-power 50Gbps PAM4 solution featuring an integrated high-performance linear driver for optics that eliminates the need for standalone components, thereby reducing system cost and complexity. The foundation of Inphi’s Polaris platform is a highly configurable DSP engine that is field proven and qualified in multiple hyperscale data center networks.
Gen2 Key Features
Field-proven PAM4 DSPs qualified in multiple hyperscale cloud data centers
Developed in 7 nm CMOS process technology
Supports short-reach multi-mode <100m and long-reach SMF 500m-40km optical interconnects
Supports 50G PAM4, 50Gbps breakout and 25G NRZ transmission
Integrates EML and Silicon Photonics linear drivers
400G x FR4
400G SR8/SR4 2
200G DR4/ FR4/SR4
Polaris Gen2 Form Factors
QSFP-DD QSFP 56
Polaris™ is the industry’s first 16nm CMOS PAM4 platform solution for hyperscale data center, service provider and enterprise networks. The foundation of Polaris is a highly configurable DSP Engine that is based on three generations of proven silicon and is designed to achieve performance levels for both multi-mode and single mode optical interconnects covering up to 10km, while keeping an extremely low power profile of optical module applications. The Polaris platform includes Inphi’s marketing-leading linear TIA and Driver.
DSP Engine with a unique mixed-mode DSP architecture for high performance, low power applications needing adaptability and configurability.
Numerous self-test and loopback modes that allow diagnostic monitoring of channel and system parameters.
Eye-scan, samplers and monitors on all receiver interfaces for link margin and stress testing along with GUI and API routines for data and error analytics.